/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Mcal_ScrBits.h                                                                             *
 *  \brief    This file contains interface header for MCU MCAL driver                                   *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2024/11/20     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef MCAL_SCRBITS_H
#define MCAL_SCRBITS_H


#ifdef __cplusplus
extern "C" {
#endif
/* PRQA S 0791 EOF */

/* Version and Check Begin */
/* Version Info Begin */
#define MCAL_SCRBITS_H_VENDOR_ID    0x8C
#define MCAL_SCRBITS_H_AR_RELEASE_MAJOR_VERSION    4
#define MCAL_SCRBITS_H_AR_RELEASE_MINOR_VERSION    3
#define MCAL_SCRBITS_H_AR_RELEASE_REVISION_VERSION 1
#define MCAL_SCRBITS_H_SW_MAJOR_VERSION    1
#define MCAL_SCRBITS_H_SW_MINOR_VERSION    0
#define MCAL_SCRBITS_H_SW_PATCH_VERSION    0
/* Version Info End */
/* Version and Check End */

#define SF_DOMAIN 0U
#define LP_DOMAIN 1U

#define TYPE_RW 0U
#define TYPE_RO 1U
#define TYPE_L16 2U
#define TYPE_L31 3U
#define TYPE_R16W16 4U

#define SCR_SF_BTI_AXI_R52P_M0_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 0, 1}
#define SCR_SF_BTI_AXI_R52P_M0_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 1, 1}
#define SCR_SF_BTI_AXI_R52P_F0_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 2, 1}
#define SCR_SF_BTI_AXI_R52P_F0_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 3, 1}
#define SCR_SF_BTI_AHB_R52_P0_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 4, 1}
#define SCR_SF_BTI_AHB_R52_P0_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 5, 1}
#define SCR_SF_BTI_AXI_R52P_M1_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 6, 1}
#define SCR_SF_BTI_AXI_R52P_M1_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 7, 1}
#define SCR_SF_BTI_AXI_R52P_F1_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 8, 1}
#define SCR_SF_BTI_AXI_R52P_F1_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 9, 1}
#define SCR_SF_BTI_AHB_R52_P1_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 10, 1}
#define SCR_SF_BTI_AHB_R52_P1_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 11, 1}
#define SCR_SF_BTI_AXI_R52P_M2_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 12, 1}
#define SCR_SF_BTI_AXI_R52P_M2_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 13, 1}
#define SCR_SF_BTI_AXI_R52P_F2_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 14, 1}
#define SCR_SF_BTI_AXI_R52P_F2_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 15, 1}
#define SCR_SF_BTI_AHB_R52_P2_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 32, 1}
#define SCR_SF_BTI_AHB_R52_P2_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 33, 1}
#define SCR_SF_BTI_AXI_R52P_M3_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 34, 1}
#define SCR_SF_BTI_AXI_R52P_M3_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 35, 1}
#define SCR_SF_BTI_AXI_R52P_F3_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 36, 1}
#define SCR_SF_BTI_AXI_R52P_F3_WRD_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 37, 1}
#define SCR_SF_BTI_AHB_R52_P3_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 38, 1}
#define SCR_SF_BTI_AHB_R52_P3_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 39, 1}
#define SCR_SF_BTI_AHB_R5_LP_P0_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 40, 1}
#define SCR_SF_BTI_AHB_R5_LP_P0_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 41, 1}
#define SCR_SF_BTI_AHB_R5_SE_P0_CHN_TIMEOUT  {SF_DOMAIN, TYPE_RO, 42, 1}
#define SCR_SF_BTI_AHB_R5_SE_P0_CHN_IDLE  {SF_DOMAIN, TYPE_RO, 43, 1}
#define SCR_SF_AXI2AHB_R52_P0_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 64, 11}
#define SCR_SF_AXI2AHB_R52_P1_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 96, 11}
#define SCR_SF_AXI2AHB_R52_P2_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 128, 11}
#define SCR_SF_AXI2AHB_R52_P3_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 160, 11}
#define SCR_SF_AXI2AHB_R5_SE_P0_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 192, 11}
#define SCR_SF_AXI2AHB_R5_LP_P0_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 224, 11}
#define SCR_SF_AXI2AHB_NOC_SAF_TO_XBSF_O_SCR_CFG  {SF_DOMAIN, TYPE_RO, 256, 11}
#define SCR_SF_FAB_SF_M_F_0_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 288, 1}
#define SCR_SF_FAB_SF_M_F_11_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 289, 1}
#define SCR_SF_FAB_SF_M_F_1_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 290, 1}
#define SCR_SF_FAB_SF_M_F_2_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 291, 1}
#define SCR_SF_FAB_SF_M_F_3_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 292, 1}
#define SCR_SF_FAB_SF_M_F_4_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 293, 1}
#define SCR_SF_FAB_SF_M_F_5_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 294, 1}
#define SCR_SF_FAB_SF_M_F_7_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 295, 1}
#define SCR_SF_FAB_SF_M_F_8_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 296, 1}
#define SCR_SF_FAB_SF_M_F_9_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 297, 1}
#define SCR_SF_FAB_SF_M_F_GPV_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 298, 1}
#define SCR_SF_FAB_SF_S_F_0_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 299, 1}
#define SCR_SF_FAB_SF_S_F_1_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 300, 1}
#define SCR_SF_FAB_SF_S_F_2_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 301, 1}
#define SCR_SF_FAB_SF_S_F_3_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 302, 1}
#define SCR_SF_FAB_SF_S_F_5_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 303, 1}
#define SCR_SF_FAB_SF_S_F_6A_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 320, 1}
#define SCR_SF_FAB_SF_S_F_6B_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 321, 1}
#define SCR_SF_FAB_SF_S_F_8_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 322, 1}
#define SCR_SF_FAB_SF_S_F_9_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 323, 1}
#define SCR_SF_FAB_SF_SVREG_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 324, 1}
#define SCR_SF_FAB_SF_SVREG_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 325, 1}
#define SCR_SF_FAB_AP_M_A_0_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 352, 1}
#define SCR_SF_FAB_AP_M_A_1_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 353, 1}
#define SCR_SF_FAB_AP_M_A_2_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 354, 1}
#define SCR_SF_FAB_AP_M_A_3_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 355, 1}
#define SCR_SF_FAB_AP_M_A_4_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 356, 1}
#define SCR_SF_FAB_AP_S_A_1_T_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 357, 1}
#define SCR_SF_FAB_AP_M_A_GPV_I_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 358, 1}
#define SCR_SF_FAB_AP_SVREG_MAINNOPENDINGTRANS  {SF_DOMAIN, TYPE_RO, 359, 1}
#define SCR_SF_CR52P_DCLSCOMPOUT_LEV_15_0  {SF_DOMAIN, TYPE_RO, 384, 16}
#define SCR_SF_CR52P_DCLSCOMPOUT_LEV_31_16  {SF_DOMAIN, TYPE_RO, 416, 16}
#define SCR_SF_CR52P_DCLSCOMPOUT_LEV_47_32  {SF_DOMAIN, TYPE_RO, 448, 16}
#define SCR_SF_CR52P_DCLSCOMPOUT_LEV_59_48  {SF_DOMAIN, TYPE_RO, 480, 12}
#define SCR_SF_CR52P_DBGACK0  {SF_DOMAIN, TYPE_RO, 492, 1}
#define SCR_SF_CR52P_DBGACK1  {SF_DOMAIN, TYPE_RO, 493, 1}
#define SCR_SF_CR52P_DBGACK2  {SF_DOMAIN, TYPE_RO, 494, 1}
#define SCR_SF_CR52P_DBGACK3  {SF_DOMAIN, TYPE_RO, 495, 1}
#define SCR_SF_CR52P_ERREVENT0_LEV_15_0  {SF_DOMAIN, TYPE_RO, 512, 16}
#define SCR_SF_CR52P_ERREVENT0_LEV_25_16  {SF_DOMAIN, TYPE_RO, 544, 10}
#define SCR_SF_CR52P_ERREVENT1_LEV_15_0  {SF_DOMAIN, TYPE_RO, 576, 16}
#define SCR_SF_CR52P_ERREVENT1_LEV_25_16  {SF_DOMAIN, TYPE_RO, 608, 10}
#define SCR_SF_CR52P_ERREVENT2_LEV_15_0  {SF_DOMAIN, TYPE_RO, 640, 16}
#define SCR_SF_CR52P_ERREVENT2_LEV_25_16  {SF_DOMAIN, TYPE_RO, 672, 10}
#define SCR_SF_CR52P_ERREVENT3_LEV_15_0  {SF_DOMAIN, TYPE_RO, 704, 16}
#define SCR_SF_CR52P_ERREVENT3_LEV_25_16  {SF_DOMAIN, TYPE_RO, 736, 10}
#define SCR_SF_CR52P_ERREVENT_LEV  {SF_DOMAIN, TYPE_RO, 768, 6}
#define SCR_SF_R52_DBG_GASKET_DBG_IRQ_STATUS  {SF_DOMAIN, TYPE_RO, 774, 4}
#define SCR_SF_CR52P_AXI_F0_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 800, 1}
#define SCR_SF_CR52P_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 801, 1}
#define SCR_SF_CR52P_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 802, 1}
#define SCR_SF_CR52P_AXI_P0_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 803, 1}
#define SCR_SF_CR52P_AXI_P0_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 804, 1}
#define SCR_SF_CR52P_AXI_F1_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 805, 1}
#define SCR_SF_CR52P_AXI_M1_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 806, 1}
#define SCR_SF_CR52P_AXI_M1_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 807, 1}
#define SCR_SF_CR52P_AXI_P1_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 808, 1}
#define SCR_SF_CR52P_AXI_P1_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 809, 1}
#define SCR_SF_CR52P_AXI_F2_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 810, 1}
#define SCR_SF_CR52P_AXI_M2_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 811, 1}
#define SCR_SF_CR52P_AXI_M2_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 812, 1}
#define SCR_SF_CR52P_AXI_P2_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 813, 1}
#define SCR_SF_CR52P_AXI_P2_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 814, 1}
#define SCR_SF_CR52P_AXI_F3_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 815, 1}
#define SCR_SF_CR52P_AXI_M3_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 832, 1}
#define SCR_SF_CR52P_AXI_M3_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 833, 1}
#define SCR_SF_CR52P_AXI_P3_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 834, 1}
#define SCR_SF_CR52P_AXI_P3_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 835, 1}
#define SCR_SF_DMA_SF1_AHB_M0_HUSER_GEN_AHB_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 836, 1}
#define SCR_SF_DMA_SF1_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 837, 1}
#define SCR_SF_DMA_SF1_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 838, 1}
#define SCR_SF_DMA_SF1_AHB_M1_HUSER_GEN_AHB_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 839, 1}
#define SCR_SF_DMA_SF1_AXI_M1_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 840, 1}
#define SCR_SF_DMA_SF1_AXI_M1_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 841, 1}
#define SCR_SF_DMA_SF2_AHB_M0_HUSER_GEN_AHB_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 842, 1}
#define SCR_SF_DMA_SF2_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 843, 1}
#define SCR_SF_DMA_SF2_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 844, 1}
#define SCR_SF_DMA_SF2_AHB_M1_HUSER_GEN_AHB_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 845, 1}
#define SCR_SF_DMA_SF2_AXI_M1_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 846, 1}
#define SCR_SF_DMA_SF2_AXI_M1_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 847, 1}
#define SCR_SF_DPE_AHB_M_HUSER_GEN_AHB_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 864, 1}
#define SCR_SF_DPE_AXI_M_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 865, 1}
#define SCR_SF_DPE_AXI_M_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 866, 1}
#define SCR_SF_SEHC1_AXI_M_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 867, 1}
#define SCR_SF_SEHC1_AXI_M_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 868, 1}
#define SCR_SF_ENET1_AXI_M_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 869, 1}
#define SCR_SF_ENET1_AXI_M_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 870, 1}
#define SCR_SF_ENET2_AXI_M_AWUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 871, 1}
#define SCR_SF_ENET2_AXI_M_ARUSER_GEN_AXI_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 872, 1}
#define SCR_SF_PTB_MST_HUSER_GEN_AHB_GASKET_ERR  {SF_DOMAIN, TYPE_RO, 873, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 896, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 897, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 898, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 899, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 900, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 901, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 902, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 903, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 904, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 905, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 906, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_O_AXI_SYNC_DOWN_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 907, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 928, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 929, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 930, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 931, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 932, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 933, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 934, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 935, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 936, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 937, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 938, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_O_AXI_SYNC_DOWN_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 939, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 960, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 961, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 962, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 963, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 964, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 965, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 966, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 967, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 968, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 969, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 970, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_O_AXI_SYNC_UP_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 971, 1}
#define SCR_SF_AXISD_MRAM1_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 992, 1}
#define SCR_SF_AXISD_MRAM1_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 993, 1}
#define SCR_SF_AXISD_MRAM1_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 994, 1}
#define SCR_SF_AXISD_MRAM1_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 995, 1}
#define SCR_SF_AXISD_MRAM1_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 996, 1}
#define SCR_SF_AXISD_MRAM1_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 997, 1}
#define SCR_SF_AXISD_MRAM1_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 998, 1}
#define SCR_SF_AXISD_MRAM1_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 999, 1}
#define SCR_SF_AXISD_MRAM1_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1000, 1}
#define SCR_SF_AXISD_MRAM1_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1001, 1}
#define SCR_SF_AXISD_MRAM1_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 1002, 1}
#define SCR_SF_AXISD_MRAM1_O_AXI_SYNC_DOWN_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 1003, 1}
#define SCR_SF_AXISD_MRAM2_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1024, 1}
#define SCR_SF_AXISD_MRAM2_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1025, 1}
#define SCR_SF_AXISD_MRAM2_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1026, 1}
#define SCR_SF_AXISD_MRAM2_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1027, 1}
#define SCR_SF_AXISD_MRAM2_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1028, 1}
#define SCR_SF_AXISD_MRAM2_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1029, 1}
#define SCR_SF_AXISD_MRAM2_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1030, 1}
#define SCR_SF_AXISD_MRAM2_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1031, 1}
#define SCR_SF_AXISD_MRAM2_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1032, 1}
#define SCR_SF_AXISD_MRAM2_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1033, 1}
#define SCR_SF_AXISD_MRAM2_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 1034, 1}
#define SCR_SF_AXISD_MRAM2_O_AXI_SYNC_DOWN_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 1035, 1}
#define SCR_SF_AXISD_MRAM3_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1056, 1}
#define SCR_SF_AXISD_MRAM3_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1057, 1}
#define SCR_SF_AXISD_MRAM3_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1058, 1}
#define SCR_SF_AXISD_MRAM3_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1059, 1}
#define SCR_SF_AXISD_MRAM3_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1060, 1}
#define SCR_SF_AXISD_MRAM3_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1061, 1}
#define SCR_SF_AXISD_MRAM3_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1062, 1}
#define SCR_SF_AXISD_MRAM3_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1063, 1}
#define SCR_SF_AXISD_MRAM3_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1064, 1}
#define SCR_SF_AXISD_MRAM3_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1065, 1}
#define SCR_SF_AXISD_MRAM3_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 1066, 1}
#define SCR_SF_AXISD_MRAM3_O_AXI_SYNC_DOWN_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 1067, 1}
#define SCR_SF_AXISD_MRAM4_O_AWREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1088, 1}
#define SCR_SF_AXISD_MRAM4_O_WREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1089, 1}
#define SCR_SF_AXISD_MRAM4_O_ARREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1090, 1}
#define SCR_SF_AXISD_MRAM4_O_RREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1091, 1}
#define SCR_SF_AXISD_MRAM4_O_BREADY_UNCERR  {SF_DOMAIN, TYPE_RO, 1092, 1}
#define SCR_SF_AXISD_MRAM4_O_AWVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1093, 1}
#define SCR_SF_AXISD_MRAM4_O_WVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1094, 1}
#define SCR_SF_AXISD_MRAM4_O_ARVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1095, 1}
#define SCR_SF_AXISD_MRAM4_O_BVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1096, 1}
#define SCR_SF_AXISD_MRAM4_O_RVALID_UNCERR  {SF_DOMAIN, TYPE_RO, 1097, 1}
#define SCR_SF_AXISD_MRAM4_O_SELFTEST_MODE_REDUNDANCY_UNCERR  {SF_DOMAIN, TYPE_RO, 1098, 1}
#define SCR_SF_AXISD_MRAM4_O_AXI_SYNC_DOWN_LKSTEP_COMP_ERR  {SF_DOMAIN, TYPE_RO, 1099, 1}
#define SCR_SF_CRAM1_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 0, 1}
#define SCR_SF_CRAM2_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 1, 1}
#define SCR_SF_CRAM3_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 2, 1}
#define SCR_SF_CRAM4_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 3, 1}
#define SCR_SF_IRAM1_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 4, 1}
#define SCR_SF_IRAM2_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 5, 1}
#define SCR_SF_IRAM3_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 6, 1}
#define SCR_SF_MRAM1_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 8, 1}
#define SCR_SF_MRAM2_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 9, 1}
#define SCR_SF_MRAM3_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 10, 1}
#define SCR_SF_MRAM4_ECC_DISABLE  {SF_DOMAIN, TYPE_L16, 11, 1}
#define SCR_SF_DMA_SF1_LOCKSTEP_DISABLE  {SF_DOMAIN, TYPE_L16, 12, 1}
#define SCR_SF_DMA_SF2_LOCKSTEP_DISABLE  {SF_DOMAIN, TYPE_L16, 13, 1}
#define SCR_SF_R52P_CFGVECTABLE0  {SF_DOMAIN, TYPE_L31, 0, 27}
#define SCR_SF_R52P_C0_VECTABLE_CFG_EN  {SF_DOMAIN, TYPE_L31, 27, 1}
#define SCR_SF_R52P_CFGVECTABLE1  {SF_DOMAIN, TYPE_L31, 32, 27}
#define SCR_SF_R52P_C1_VECTABLE_CFG_EN  {SF_DOMAIN, TYPE_L31, 59, 1}
#define SCR_SF_R52P_CFGVECTABLE2  {SF_DOMAIN, TYPE_L31, 64, 27}
#define SCR_SF_R52P_C2_VECTABLE_CFG_EN  {SF_DOMAIN, TYPE_L31, 91, 1}
#define SCR_SF_R52P_CFGVECTABLE3  {SF_DOMAIN, TYPE_L31, 96, 27}
#define SCR_SF_R52P_C3_VECTABLE_CFG_EN  {SF_DOMAIN, TYPE_L31, 123, 1}
#define SCR_SF_XSPI1_SRC_CFG_SWAP  {SF_DOMAIN, TYPE_L31, 128, 1}
#define SCR_SF_XSPI1_SRC_CFG_PARALLEL_MODE  {SF_DOMAIN, TYPE_L31, 129, 1}
#define SCR_SF_XSPI1_SRC_CFG_LOCKSTEP_MODE  {SF_DOMAIN, TYPE_L31, 130, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_INIT_REG  {SF_DOMAIN, TYPE_RW, 0, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_DBG_ROM_ADDRV  {SF_DOMAIN, TYPE_RW, 1, 1}
#define SCR_SF_R52_DBG_GASKET_HW_DBG_EN  {SF_DOMAIN, TYPE_RW, 2, 4}
#define SCR_SF_R52_DBG_GASKET_DBG_IRQ_STATUS_EN  {SF_DOMAIN, TYPE_RW, 6, 4}
#define SCR_SF_R52P_CPUHALT0  {SF_DOMAIN, TYPE_RW, 32, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_L1_CACHE_INV_DIS0  {SF_DOMAIN, TYPE_RW, 33, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_SAFETY_BOOT0  {SF_DOMAIN, TYPE_RW, 34, 1}
#define SCR_SF_VMUX_CR52P_AXI_M0_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 36, 1}
#define SCR_SF_VMUX_CR52P_AXI_M0_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 36, 1}
#define SCR_SF_VMUX_CR52P_AXI_P0_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 36, 1}
#define SCR_SF_VMUX_CR52P_AXI_P0_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 36, 1}
#define SCR_SF_VMUX_CR52P_AXI_F0_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 36, 1}
#define SCR_SF_VMUX_CR52P_AXI_M0_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 37, 3}
#define SCR_SF_VMUX_CR52P_AXI_M0_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 37, 3}
#define SCR_SF_VMUX_CR52P_AXI_P0_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 37, 3}
#define SCR_SF_VMUX_CR52P_AXI_P0_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 37, 3}
#define SCR_SF_CR52P_C0_AXVMID  {SF_DOMAIN, TYPE_RW, 40, 3}
#define SCR_SF_MB_SYNC_R52P_CFG_CPU_HALT1  {SF_DOMAIN, TYPE_RW, 64, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_L1_CACHE_INV_DIS1  {SF_DOMAIN, TYPE_RW, 65, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_SAFETY_BOOT1  {SF_DOMAIN, TYPE_RW, 66, 1}
#define SCR_SF_VMUX_CR52P_AXI_M1_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 68, 1}
#define SCR_SF_VMUX_CR52P_AXI_M1_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 68, 1}
#define SCR_SF_VMUX_CR52P_AXI_P1_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 68, 1}
#define SCR_SF_VMUX_CR52P_AXI_P1_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 68, 1}
#define SCR_SF_VMUX_CR52P_AXI_F1_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 68, 1}
#define SCR_SF_VMUX_CR52P_AXI_M1_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 69, 3}
#define SCR_SF_VMUX_CR52P_AXI_M1_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 69, 3}
#define SCR_SF_VMUX_CR52P_AXI_P1_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 69, 3}
#define SCR_SF_VMUX_CR52P_AXI_P1_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 69, 3}
#define SCR_SF_CR52P_C1_AXVMID  {SF_DOMAIN, TYPE_RW, 72, 3}
#define SCR_SF_MB_SYNC_R52P_CFG_CPU_HALT2  {SF_DOMAIN, TYPE_RW, 96, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_L1_CACHE_INV_DIS2  {SF_DOMAIN, TYPE_RW, 97, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_AFETYBOOT2  {SF_DOMAIN, TYPE_RW, 98, 1}
#define SCR_SF_VMUX_CR52P_AXI_M2_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 100, 1}
#define SCR_SF_VMUX_CR52P_AXI_M2_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 100, 1}
#define SCR_SF_VMUX_CR52P_AXI_P2_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 100, 1}
#define SCR_SF_VMUX_CR52P_AXI_P2_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 100, 1}
#define SCR_SF_VMUX_CR52P_AXI_F2_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 100, 1}
#define SCR_SF_VMUX_CR52P_AXI_M2_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 101, 3}
#define SCR_SF_VMUX_CR52P_AXI_M2_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 101, 3}
#define SCR_SF_VMUX_CR52P_AXI_P2_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 101, 3}
#define SCR_SF_VMUX_CR52P_AXI_P2_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 101, 3}
#define SCR_SF_CR52P_C2_AXVMID  {SF_DOMAIN, TYPE_RW, 104, 3}
#define SCR_SF_MB_SYNC_R52P_CFG_CPU_HALT3  {SF_DOMAIN, TYPE_RW, 128, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_L1_CACHE_INV_DIS3  {SF_DOMAIN, TYPE_RW, 129, 1}
#define SCR_SF_MB_SYNC_R52P_CFG_SAFETY_BOOT3  {SF_DOMAIN, TYPE_RW, 130, 1}
#define SCR_SF_VMUX_CR52P_AXI_M3_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 132, 1}
#define SCR_SF_VMUX_CR52P_AXI_M3_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 132, 1}
#define SCR_SF_VMUX_CR52P_AXI_P3_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 132, 1}
#define SCR_SF_VMUX_CR52P_AXI_P3_AWUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 132, 1}
#define SCR_SF_VMUX_CR52P_AXI_F3_ARUSER_GEN_CFG_R52_MODE  {SF_DOMAIN, TYPE_RW, 132, 1}
#define SCR_SF_VMUX_CR52P_AXI_M3_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 133, 3}
#define SCR_SF_VMUX_CR52P_AXI_M3_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 133, 3}
#define SCR_SF_VMUX_CR52P_AXI_P3_ARUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 133, 3}
#define SCR_SF_VMUX_CR52P_AXI_P3_AWUSER_GEN_CFG_ID_SEL  {SF_DOMAIN, TYPE_RW, 133, 3}
#define SCR_SF_CR52P_C3_AXVMID  {SF_DOMAIN, TYPE_RW, 136, 3}
#define SCR_SF_XTRG1_OE_GASKET_SCR_OE_31_0  {SF_DOMAIN, TYPE_RW, 224, 32}
#define SCR_SF_XTRG1_OE_GASKET_SCR_OE_63_32  {SF_DOMAIN, TYPE_RW, 256, 32}
#define SCR_SF_XTRG2_OE_GASKET_SCR_OE_31_0  {SF_DOMAIN, TYPE_RW, 288, 32}
#define SCR_SF_XTRG2_OE_GASKET_SCR_OE_63_32  {SF_DOMAIN, TYPE_RW, 320, 32}
#define SCR_SF_ETMR1_LP_MODE  {SF_DOMAIN, TYPE_RW, 352, 1}
#define SCR_SF_ETMR2_LP_MODE  {SF_DOMAIN, TYPE_RW, 384, 1}
#define SCR_SF_ETMR3_LP_MODE  {SF_DOMAIN, TYPE_RW, 416, 1}
#define SCR_SF_ETMR4_LP_MODE  {SF_DOMAIN, TYPE_RW, 448, 1}
#define SCR_SF_XSPI1_SCLK_PA_GPIO_MUX_I_SCR_XSPI_SEL  {SF_DOMAIN, TYPE_RW, 480, 1}
#define SCR_SF_XSPI1_SCLK_PB_GPIO_MUX_I_SCR_XSPI_SEL  {SF_DOMAIN, TYPE_RW, 481, 1}
#define SCR_SF_MB_VMSTR_MUX_MB_R52_VM_EN  {SF_DOMAIN, TYPE_RW, 512, 1}
#define SCR_SF_MB_VMSTR_MUX_CFG_CPU_RST_B  {SF_DOMAIN, TYPE_RW, 513, 8}
#define SCR_SF_CANFD3_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 544, 1}
#define SCR_SF_CANFD4_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 576, 1}
#define SCR_SF_CANFD5_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 608, 1}
#define SCR_SF_CANFD6_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 640, 1}
#define SCR_SF_CANFD7_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 672, 1}
#define SCR_SF_CANFD8_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 704, 1}
#define SCR_SF_CANFD9_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 736, 1}
#define SCR_SF_CANFD10_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 768, 1}
#define SCR_SF_CANFD11_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 800, 1}
#define SCR_SF_CANFD12_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 832, 1}
#define SCR_SF_CANFD13_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 864, 1}
#define SCR_SF_CANFD14_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 896, 1}
#define SCR_SF_CANFD15_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 928, 1}
#define SCR_SF_CANFD16_STOP_DOZE_SEL  {SF_DOMAIN, TYPE_RW, 960, 1}
#define SCR_SF_SCAN_MUX_BGR33_SF_REG0  {SF_DOMAIN, TYPE_RW, 992, 11}
#define SCR_SF_SCAN_MUX_BGR33_SF_TEST  {SF_DOMAIN, TYPE_RW, 1003, 3}
#define SCR_SF_SCAN_MUX_BGR33_SF_BGSEL  {SF_DOMAIN, TYPE_RW, 1006, 5}
#define SCR_SF_BGR33_SF_TRIM_SEL  {SF_DOMAIN, TYPE_RW, 1011, 1}
#define SCR_SF_SOC_DBG_GASKET_SF_SW_CORE_DBG_EN  {SF_DOMAIN, TYPE_RW, 1024, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_I2C2  {SF_DOMAIN, TYPE_RW, 1032, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_I2C3  {SF_DOMAIN, TYPE_RW, 1040, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_I2C4  {SF_DOMAIN, TYPE_RW, 1048, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART3  {SF_DOMAIN, TYPE_RW, 1056, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART4  {SF_DOMAIN, TYPE_RW, 1064, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART5  {SF_DOMAIN, TYPE_RW, 1072, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART6  {SF_DOMAIN, TYPE_RW, 1080, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART7  {SF_DOMAIN, TYPE_RW, 1088, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART8  {SF_DOMAIN, TYPE_RW, 1096, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART9  {SF_DOMAIN, TYPE_RW, 1104, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART10  {SF_DOMAIN, TYPE_RW, 1112, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART11  {SF_DOMAIN, TYPE_RW, 1120, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART12  {SF_DOMAIN, TYPE_RW, 1128, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART13  {SF_DOMAIN, TYPE_RW, 1136, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART14  {SF_DOMAIN, TYPE_RW, 1144, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART15  {SF_DOMAIN, TYPE_RW, 1152, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART16  {SF_DOMAIN, TYPE_RW, 1160, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART17  {SF_DOMAIN, TYPE_RW, 1168, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART18  {SF_DOMAIN, TYPE_RW, 1176, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART19  {SF_DOMAIN, TYPE_RW, 1184, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_UART20  {SF_DOMAIN, TYPE_RW, 1192, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI3  {SF_DOMAIN, TYPE_RW, 1200, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI4  {SF_DOMAIN, TYPE_RW, 1208, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI5  {SF_DOMAIN, TYPE_RW, 1216, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI6  {SF_DOMAIN, TYPE_RW, 1224, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI7  {SF_DOMAIN, TYPE_RW, 1232, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI8  {SF_DOMAIN, TYPE_RW, 1240, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI9  {SF_DOMAIN, TYPE_RW, 1248, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI10  {SF_DOMAIN, TYPE_RW, 1256, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI11  {SF_DOMAIN, TYPE_RW, 1264, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI12  {SF_DOMAIN, TYPE_RW, 1272, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI13  {SF_DOMAIN, TYPE_RW, 1280, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SPI14  {SF_DOMAIN, TYPE_RW, 1288, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM3  {SF_DOMAIN, TYPE_RW, 1296, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM4  {SF_DOMAIN, TYPE_RW, 1304, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM5  {SF_DOMAIN, TYPE_RW, 1312, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM6  {SF_DOMAIN, TYPE_RW, 1320, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM7  {SF_DOMAIN, TYPE_RW, 1328, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM8  {SF_DOMAIN, TYPE_RW, 1336, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM9  {SF_DOMAIN, TYPE_RW, 1344, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM10  {SF_DOMAIN, TYPE_RW, 1352, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM11  {SF_DOMAIN, TYPE_RW, 1360, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_BTM12  {SF_DOMAIN, TYPE_RW, 1368, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_WDT2  {SF_DOMAIN, TYPE_RW, 1376, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_WDT3  {SF_DOMAIN, TYPE_RW, 1384, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_WDT4  {SF_DOMAIN, TYPE_RW, 1392, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_WDT5  {SF_DOMAIN, TYPE_RW, 1400, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_WDT6  {SF_DOMAIN, TYPE_RW, 1408, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_WDT8  {SF_DOMAIN, TYPE_RW, 1416, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ADC1  {SF_DOMAIN, TYPE_RW, 1424, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ADC2  {SF_DOMAIN, TYPE_RW, 1432, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ADC3  {SF_DOMAIN, TYPE_RW, 1440, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ADC4  {SF_DOMAIN, TYPE_RW, 1448, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ADC5  {SF_DOMAIN, TYPE_RW, 1456, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ADC6  {SF_DOMAIN, TYPE_RW, 1464, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_DMA_SF1  {SF_DOMAIN, TYPE_RW, 1472, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_DMA_SF2  {SF_DOMAIN, TYPE_RW, 1480, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_DPE  {SF_DOMAIN, TYPE_RW, 1488, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_XTRG1  {SF_DOMAIN, TYPE_RW, 1496, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_XTRG2  {SF_DOMAIN, TYPE_RW, 1504, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ETMR1  {SF_DOMAIN, TYPE_RW, 1512, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ETMR2  {SF_DOMAIN, TYPE_RW, 1520, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ETMR3  {SF_DOMAIN, TYPE_RW, 1528, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_ETMR4  {SF_DOMAIN, TYPE_RW, 1536, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_EPWM1  {SF_DOMAIN, TYPE_RW, 1544, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_EPWM2  {SF_DOMAIN, TYPE_RW, 1552, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_EPWM3  {SF_DOMAIN, TYPE_RW, 1560, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_EPWM4  {SF_DOMAIN, TYPE_RW, 1568, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SENT  {SF_DOMAIN, TYPE_RW, 1576, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_SACI1  {SF_DOMAIN, TYPE_RW, 1584, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD3  {SF_DOMAIN, TYPE_RW, 1592, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD4  {SF_DOMAIN, TYPE_RW, 1600, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD5  {SF_DOMAIN, TYPE_RW, 1608, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD6  {SF_DOMAIN, TYPE_RW, 1616, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD7  {SF_DOMAIN, TYPE_RW, 1624, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD8  {SF_DOMAIN, TYPE_RW, 1632, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD9  {SF_DOMAIN, TYPE_RW, 1640, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD10  {SF_DOMAIN, TYPE_RW, 1648, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD11  {SF_DOMAIN, TYPE_RW, 1656, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD12  {SF_DOMAIN, TYPE_RW, 1664, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD13  {SF_DOMAIN, TYPE_RW, 1672, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD14  {SF_DOMAIN, TYPE_RW, 1680, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD15  {SF_DOMAIN, TYPE_RW, 1688, 6}
#define SCR_SF_SOC_DBG_GASKET_SF_IP_DBG_EN_CANFD16  {SF_DOMAIN, TYPE_RW, 1696, 6}
#define SCR_SF_LDO50TO33_DFT_MUX_IO_SF_ATEST_SEL  {SF_DOMAIN, TYPE_RW, 1760, 2}
#define SCR_SF_LDO50TO33_DFT_MUX_IO_SF_ATESTEN  {SF_DOMAIN, TYPE_RW, 1762, 1}
#define SCR_SF_LDO50TO33_DFT_MUX_IO_SF_SW_OVR_EN  {SF_DOMAIN, TYPE_RW, 1763, 1}
#define SCR_SF_LDO50TO33_DFT_MUX_IO_SF_SW_CFG  {SF_DOMAIN, TYPE_RW, 1764, 1}
#define SCR_SF_LDO50TO33_DFT_MUX_IO_SF_REG_EN  {SF_DOMAIN, TYPE_RW, 1765, 1}
#define SCR_SF_LDO50TO33_DFT_MUX_IO_SF_TR  {SF_DOMAIN, TYPE_RW, 1766, 6}
#define SCR_SF_DFT_MUX_COMB_IO_SF_TEST_EN  {SF_DOMAIN, TYPE_RW, 1772, 1}
#define SCR_SF_DFT_MUX_COMB_IO_SF_TEST_SEL  {SF_DOMAIN, TYPE_RW, 1773, 1}
#define SCR_SF_AXI2AHB_R52_P0_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1792, 11}
#define SCR_SF_AXI2AHB_R52_P1_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1824, 11}
#define SCR_SF_AXI2AHB_R52_P2_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1856, 11}
#define SCR_SF_AXI2AHB_R52_P3_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1888, 11}
#define SCR_SF_AXI2AHB_R5_SE_P0_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1920, 11}
#define SCR_SF_AXI2AHB_R5_LP_P0_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1952, 11}
#define SCR_SF_AXI2AHB_NOC_SAF_TO_XBSF_I_SCR_CFG  {SF_DOMAIN, TYPE_RW, 1984, 11}
#define SCR_SF_RESERVED_ADDR63  {SF_DOMAIN, TYPE_RW, 2016, 32}
#define SCR_SF_BTI_AXI_R52P_M0_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2048, 8}
#define SCR_SF_BTI_AXI_R52P_M1_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2048, 8}
#define SCR_SF_BTI_AXI_R52P_M2_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2048, 8}
#define SCR_SF_BTI_AXI_R52P_M3_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2048, 8}
#define SCR_SF_BTI_AXI_R52P_M0_BTI_EN  {SF_DOMAIN, TYPE_RW, 2056, 1}
#define SCR_SF_BTI_AXI_R52P_M1_BTI_EN  {SF_DOMAIN, TYPE_RW, 2057, 1}
#define SCR_SF_BTI_AXI_R52P_M2_BTI_EN  {SF_DOMAIN, TYPE_RW, 2058, 1}
#define SCR_SF_BTI_AXI_R52P_M3_BTI_EN  {SF_DOMAIN, TYPE_RW, 2059, 1}
#define SCR_SF_BTI_AXI_R52P_F0_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2080, 8}
#define SCR_SF_BTI_AXI_R52P_F1_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2080, 8}
#define SCR_SF_BTI_AXI_R52P_F2_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2080, 8}
#define SCR_SF_BTI_AXI_R52P_F3_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2080, 8}
#define SCR_SF_BTI_AXI_R52P_F0_BTI_EN  {SF_DOMAIN, TYPE_RW, 2088, 1}
#define SCR_SF_BTI_AXI_R52P_F1_BTI_EN  {SF_DOMAIN, TYPE_RW, 2089, 1}
#define SCR_SF_BTI_AXI_R52P_F2_BTI_EN  {SF_DOMAIN, TYPE_RW, 2090, 1}
#define SCR_SF_BTI_AXI_R52P_F3_BTI_EN  {SF_DOMAIN, TYPE_RW, 2091, 1}
#define SCR_SF_BTI_AHB_R52_P0_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2112, 8}
#define SCR_SF_BTI_AHB_R52_P1_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2112, 8}
#define SCR_SF_BTI_AHB_R52_P2_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2112, 8}
#define SCR_SF_BTI_AHB_R52_P3_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2112, 8}
#define SCR_SF_BTI_AHB_R52_P0_BTI_EN  {SF_DOMAIN, TYPE_RW, 2120, 1}
#define SCR_SF_BTI_AHB_R52_P2_BTI_EN  {SF_DOMAIN, TYPE_RW, 2121, 1}
#define SCR_SF_BTI_AHB_R52_P1_BTI_EN  {SF_DOMAIN, TYPE_RW, 2122, 1}
#define SCR_SF_BTI_AHB_R52_P3_BTI_EN  {SF_DOMAIN, TYPE_RW, 2123, 1}
#define SCR_SF_BTI_AHB_R5_SE_P0_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2144, 8}
#define SCR_SF_BTI_AHB_R5_SE_P0_BTI_EN  {SF_DOMAIN, TYPE_RW, 2152, 1}
#define SCR_SF_BTI_AHB_R5_LP_P0_TIMEOUT_DIV  {SF_DOMAIN, TYPE_RW, 2176, 8}
#define SCR_SF_BTI_AHB_R5_LP_P0_BTI_EN  {SF_DOMAIN, TYPE_RW, 2184, 1}
#define SCR_SF_BTI_AXI_R52P_M0_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2208, 1}
#define SCR_SF_BTI_AXI_R52P_M0_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2209, 1}
#define SCR_SF_BTI_AXI_R52P_M0_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2210, 1}
#define SCR_SF_BTI_AXI_R52P_M0_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2211, 1}
#define SCR_SF_BTI_AXI_R52P_M1_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2212, 1}
#define SCR_SF_BTI_AXI_R52P_M1_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2213, 1}
#define SCR_SF_BTI_AXI_R52P_M1_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2214, 1}
#define SCR_SF_BTI_AXI_R52P_M1_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2215, 1}
#define SCR_SF_BTI_AXI_R52P_M2_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2216, 1}
#define SCR_SF_BTI_AXI_R52P_M2_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2217, 1}
#define SCR_SF_BTI_AXI_R52P_M2_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2218, 1}
#define SCR_SF_BTI_AXI_R52P_M2_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2219, 1}
#define SCR_SF_BTI_AXI_R52P_M3_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2220, 1}
#define SCR_SF_BTI_AXI_R52P_M3_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2221, 1}
#define SCR_SF_BTI_AXI_R52P_M3_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2222, 1}
#define SCR_SF_BTI_AXI_R52P_M3_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2223, 1}
#define SCR_SF_BTI_AXI_R52P_F0_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2224, 1}
#define SCR_SF_BTI_AXI_R52P_F0_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2225, 1}
#define SCR_SF_BTI_AXI_R52P_F0_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2226, 1}
#define SCR_SF_BTI_AXI_R52P_F0_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2227, 1}
#define SCR_SF_BTI_AXI_R52P_F1_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2228, 1}
#define SCR_SF_BTI_AXI_R52P_F1_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2229, 1}
#define SCR_SF_BTI_AXI_R52P_F1_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2230, 1}
#define SCR_SF_BTI_AXI_R52P_F1_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2231, 1}
#define SCR_SF_BTI_AXI_R52P_F2_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2232, 1}
#define SCR_SF_BTI_AXI_R52P_F2_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2233, 1}
#define SCR_SF_BTI_AXI_R52P_F2_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2234, 1}
#define SCR_SF_BTI_AXI_R52P_F2_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2235, 1}
#define SCR_SF_BTI_AXI_R52P_F3_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2236, 1}
#define SCR_SF_BTI_AXI_R52P_F3_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2237, 1}
#define SCR_SF_BTI_AXI_R52P_F3_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2238, 1}
#define SCR_SF_BTI_AXI_R52P_F3_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2239, 1}
#define SCR_SF_BTI_AHB_R52_P0_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2240, 1}
#define SCR_SF_BTI_AHB_R52_P0_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2241, 1}
#define SCR_SF_BTI_AHB_R52_P1_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2242, 1}
#define SCR_SF_BTI_AHB_R52_P1_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2243, 1}
#define SCR_SF_BTI_AHB_R52_P2_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2244, 1}
#define SCR_SF_BTI_AHB_R52_P2_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2245, 1}
#define SCR_SF_BTI_AHB_R52_P3_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2246, 1}
#define SCR_SF_BTI_AHB_R52_P3_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2247, 1}
#define SCR_SF_BTI_AHB_R5_SE_P0_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2248, 1}
#define SCR_SF_BTI_AHB_R5_SE_P0_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2249, 1}
#define SCR_SF_BTI_AHB_R5_LP_P0_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2250, 1}
#define SCR_SF_BTI_AHB_R5_LP_P0_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2251, 1}
#define SCR_SF_AXI2AHB_R52_P0_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2272, 1}
#define SCR_SF_AXI2AHB_R52_P1_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2273, 1}
#define SCR_SF_AXI2AHB_R52_P2_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2274, 1}
#define SCR_SF_AXI2AHB_R52_P3_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2275, 1}
#define SCR_SF_AXI2AHB_R5_SE_P0_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2276, 1}
#define SCR_SF_AXI2AHB_R5_LP_P0_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2277, 1}
#define SCR_SF_AXI2AHB_NOC_SAF_TO_XBSF_I_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2278, 1}
#define SCR_SF_AAXI_MST_R5_LP_P0_UNC_ERR_ENABLE  {SF_DOMAIN, TYPE_RW, 2304, 1}
#define SCR_SF_AAXI_MST_R5_LP_P0_UNC_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2305, 1}
#define SCR_SF_AAXI_SLV_R5_LP_P0_UNC_ERR_ENABLE  {SF_DOMAIN, TYPE_RW, 2304, 1}
#define SCR_SF_AAXI_SLV_R5_LP_P0_UNC_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2305, 1}
#define SCR_SF_AAXI_MST_AXB_R52A_TO_AXB_LP_UNC_ERR_ENABLE  {SF_DOMAIN, TYPE_RW, 2306, 1}
#define SCR_SF_AAXI_MST_AXB_R52A_TO_AXB_LP_UNC_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2307, 1}
#define SCR_SF_AAXI_SLV_AXB_R52A_TO_AXB_LP_UNC_ERR_ENABLE  {SF_DOMAIN, TYPE_RW, 2306, 1}
#define SCR_SF_AAXI_SLV_AXB_R52A_TO_AXB_LP_UNC_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2307, 1}
#define SCR_SF_AAXI_MST_AXB_LP_TO_AXB_R52A_UNC_ERR_ENABLE  {SF_DOMAIN, TYPE_RW, 2308, 1}
#define SCR_SF_AAXI_MST_AXB_LP_TO_AXB_R52A_UNC_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2309, 1}
#define SCR_SF_AAXI_SLV_AXB_LP_TO_AXB_R52A_UNC_ERR_ENABLE  {SF_DOMAIN, TYPE_RW, 2308, 1}
#define SCR_SF_AAXI_SLV_AXB_LP_TO_AXB_R52A_UNC_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2309, 1}
#define SCR_SF_AHB2APB3_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2336, 1}
#define SCR_SF_AHB2APB3_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2337, 1}
#define SCR_SF_AHB2APB3_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2338, 1}
#define SCR_SF_AHB2APB3_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2339, 1}
#define SCR_SF_AHB2APB4_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2340, 1}
#define SCR_SF_AHB2APB4_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2341, 1}
#define SCR_SF_AHB2APB4_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2342, 1}
#define SCR_SF_AHB2APB4_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2343, 1}
#define SCR_SF_AHB2APB5_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2344, 1}
#define SCR_SF_AHB2APB5_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2345, 1}
#define SCR_SF_AHB2APB5_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2346, 1}
#define SCR_SF_AHB2APB5_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2347, 1}
#define SCR_SF_AHB2APB6_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2348, 1}
#define SCR_SF_AHB2APB6_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2349, 1}
#define SCR_SF_AHB2APB6_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2350, 1}
#define SCR_SF_AHB2APB6_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2351, 1}
#define SCR_SF_AHB2APB7_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2352, 1}
#define SCR_SF_AHB2APB7_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2353, 1}
#define SCR_SF_AHB2APB7_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2354, 1}
#define SCR_SF_AHB2APB7_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2355, 1}
#define SCR_SF_AHB2APB2_XBSF_COR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2356, 1}
#define SCR_SF_AHB2APB2_XBSF_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2357, 1}
#define SCR_SF_AHB2APB2_XBSF_COR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2358, 1}
#define SCR_SF_AHB2APB2_XBSF_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2359, 1}
#define SCR_SF_AAPB_MST_APBMUX5_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2368, 1}
#define SCR_SF_AAPB_MST_APBMUX5_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2369, 1}
#define SCR_SF_AAPB_MST_APBMUX6_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2370, 1}
#define SCR_SF_AAPB_MST_APBMUX6_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2371, 1}
#define SCR_SF_AAPB_MST_APBMUX7_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2372, 1}
#define SCR_SF_AAPB_MST_APBMUX7_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2373, 1}
#define SCR_SF_AAPB_MST_MAC_TO_CPU_MIX_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2374, 1}
#define SCR_SF_AAPB_MST_MAC_TO_CPU_MIX_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2375, 1}
#define SCR_SF_AAPB_MST_MAC_TO_LPP_MIX_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2376, 1}
#define SCR_SF_AAPB_MST_MAC_TO_LPP_MIX_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2377, 1}
#define SCR_SF_AAPB_MST_MAC_TO_SF_BOOT_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2378, 1}
#define SCR_SF_AAPB_MST_MAC_TO_SF_BOOT_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2379, 1}
#define SCR_SF_AAPB_MST_MAC_TO_SF_MAIN_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2380, 1}
#define SCR_SF_AAPB_MST_MAC_TO_SF_MAIN_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2381, 1}
#define SCR_SF_AAPB_SLV_MAC_TO_CPU_MIX_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2382, 1}
#define SCR_SF_AAPB_SLV_MAC_TO_CPU_MIX_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2383, 1}
#define SCR_SF_AAPB_SLV_MAC_TO_SF_BOOT_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2384, 1}
#define SCR_SF_AAPB_SLV_MAC_TO_SF_BOOT_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2385, 1}
#define SCR_SF_AAPB_SLV_MAC_TO_SF_MAIN_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2386, 1}
#define SCR_SF_AAPB_SLV_MAC_TO_SF_MAIN_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2387, 1}
#define SCR_SF_AAPB_SLV_APBMUX5_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2388, 1}
#define SCR_SF_AAPB_SLV_APBMUX5_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2389, 1}
#define SCR_SF_AAPB_SLV_APBMUX6_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2390, 1}
#define SCR_SF_AAPB_SLV_APBMUX6_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2391, 1}
#define SCR_SF_AAPB_MST_XBSF_TO_APBMUX2_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2392, 1}
#define SCR_SF_AAPB_MST_XBSF_TO_APBMUX2_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2393, 1}
#define SCR_SF_AAPB_MST_APBMUXX_TO_CPU_MIX_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2394, 1}
#define SCR_SF_AAPB_MST_APBMUXX_TO_CPU_MIX_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2395, 1}
#define SCR_SF_AAPB_MST_APBMUXX_TO_SF_TOP_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2396, 1}
#define SCR_SF_AAPB_MST_APBMUXX_TO_SF_TOP_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2397, 1}
#define SCR_SF_AAPB_MST_APBMUXX_TO_SF_TOP_24M_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2398, 1}
#define SCR_SF_AAPB_MST_APBMUXX_TO_SF_TOP_24M_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2399, 1}
#define SCR_SF_AAPB_SLV_APBMUXX_TO_CPU_MIX_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2400, 1}
#define SCR_SF_AAPB_SLV_APBMUXX_TO_CPU_MIX_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2401, 1}
#define SCR_SF_AAPB_SLV_APBMUXX_TO_SF_TOP_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2402, 1}
#define SCR_SF_AAPB_SLV_APBMUXX_TO_SF_TOP_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2403, 1}
#define SCR_SF_AAPB_SLV_APBMUXX_TO_SF_TOP_24M_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2404, 1}
#define SCR_SF_AAPB_SLV_APBMUXX_TO_SF_TOP_24M_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2405, 1}
#define SCR_SF_AAPB_MST_IRAMC1_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2406, 1}
#define SCR_SF_AAPB_MST_IRAMC1_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2407, 1}
#define SCR_SF_AAPB_MST_IRAMC2_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2408, 1}
#define SCR_SF_AAPB_MST_IRAMC2_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2409, 1}
#define SCR_SF_AAPB_MST_IRAMC3_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2410, 1}
#define SCR_SF_AAPB_MST_IRAMC3_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2411, 1}
#define SCR_SF_AAPB_SLV_IRAMC1_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2412, 1}
#define SCR_SF_AAPB_SLV_IRAMC1_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2413, 1}
#define SCR_SF_AAPB_SLV_IRAMC2_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2414, 1}
#define SCR_SF_AAPB_SLV_IRAMC2_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2415, 1}
#define SCR_SF_AAPB_SLV_IRAMC3_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2416, 1}
#define SCR_SF_AAPB_SLV_IRAMC3_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2417, 1}
#define SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2418, 1}
#define SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2419, 1}
#define SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2420, 1}
#define SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2421, 1}
#define SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2422, 1}
#define SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2423, 1}
#define SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2424, 1}
#define SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2425, 1}
#define SCR_SF_AAPB_SLV_APBMUX7_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2426, 1}
#define SCR_SF_AAPB_SLV_APBMUX7_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2427, 1}
#define SCR_SF_MPC_XSPI1A_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2428, 1}
#define SCR_SF_MPC_XSPI1A_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2429, 1}
#define SCR_SF_MPC_XSPI1A_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2430, 1}
#define SCR_SF_MPC_XSPI1A_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2431, 1}
#define SCR_SF_MPC_XSPI1B_SRC_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2432, 1}
#define SCR_SF_MPC_XSPI1B_SRC_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2433, 1}
#define SCR_SF_MPC_XSPI1B_DST_IRQ_ENB  {SF_DOMAIN, TYPE_RW, 2434, 1}
#define SCR_SF_MPC_XSPI1B_DST_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2435, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2464, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2465, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2466, 1}
/* PRQA S 0793 1 */
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2467, 1}
#define SCR_SF_AXISD_AXB_R52A_TO_NOC_SF_I_AXI_SYNC_DOWN_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2468, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2496, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2497, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2498, 1}
/* PRQA S 0793 1 */
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2499, 1}
#define SCR_SF_AXISD_AXB_R52B_TO_NOC_SF_I_AXI_SYNC_DOWN_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2500, 1}
#define SCR_SF_AXISD_MRAM1_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2528, 1}
#define SCR_SF_AXISD_MRAM1_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2529, 1}
#define SCR_SF_AXISD_MRAM1_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2530, 1}
#define SCR_SF_AXISD_MRAM1_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2531, 1}
#define SCR_SF_AXISD_MRAM1_I_AXI_SYNC_DOWN_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2532, 1}
#define SCR_SF_AXISD_MRAM2_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2560, 1}
#define SCR_SF_AXISD_MRAM2_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2561, 1}
#define SCR_SF_AXISD_MRAM2_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2562, 1}
#define SCR_SF_AXISD_MRAM2_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2563, 1}
#define SCR_SF_AXISD_MRAM2_I_AXI_SYNC_DOWN_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2564, 1}
#define SCR_SF_AXISD_MRAM3_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2592, 1}
#define SCR_SF_AXISD_MRAM3_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2593, 1}
#define SCR_SF_AXISD_MRAM3_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2594, 1}
#define SCR_SF_AXISD_MRAM3_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2595, 1}
#define SCR_SF_AXISD_MRAM3_I_AXI_SYNC_DOWN_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2596, 1}
#define SCR_SF_AXISD_MRAM4_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2624, 1}
#define SCR_SF_AXISD_MRAM4_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2625, 1}
#define SCR_SF_AXISD_MRAM4_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2626, 1}
#define SCR_SF_AXISD_MRAM4_I_AXI_SYNC_DOWN_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2627, 1}
#define SCR_SF_AXISD_MRAM4_I_AXI_SYNC_DOWN_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2628, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_I_AXI_UNCERR_EN  {SF_DOMAIN, TYPE_RW, 2656, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_I_AXI_UNCERR_CLR  {SF_DOMAIN, TYPE_RW, 2657, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_I_AXI_SYNC_UP_LKSTEP_COMP_ERR_EN  {SF_DOMAIN, TYPE_RW, 2658, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_I_AXI_SYNC_UP_LKSTEP_COMP_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2659, 1}
#define SCR_SF_AXISU_NOC_SF_TO_AXB_R52B_I_AXI_SYNC_UP_UNC_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2660, 1}
#define SCR_SF_FAB_SF_FIREWALL_AP_MAINFW_ENABLE  {SF_DOMAIN, TYPE_RW, 2688, 1}
#define SCR_SF_FAB_SF_FIREWALL_HSM_MAINFW_ENABLE  {SF_DOMAIN, TYPE_RW, 2689, 1}
#define SCR_SF_FAB_SF_FIREWALL_LPP_MAINFW_ENABLE  {SF_DOMAIN, TYPE_RW, 2690, 1}
#define SCR_SF_CR52P_SCR_FAULT_CHK_EN0  {SF_DOMAIN, TYPE_RW, 2720, 7}
#define SCR_SF_CR52P_SCR_FAULT_CHK_EN1  {SF_DOMAIN, TYPE_RW, 2727, 7}
#define SCR_SF_CR52P_SCR_FAULT_CHK_EN2  {SF_DOMAIN, TYPE_RW, 2734, 7}
#define SCR_SF_CR52P_SCR_FAULT_CHK_EN3  {SF_DOMAIN, TYPE_RW, 2741, 7}
#define SCR_SF_CR52P_SCR_FAULT_CHK_EN_GLB  {SF_DOMAIN, TYPE_RW, 2748, 2}
#define SCR_SF_CR52P_SCR_R52_CORE_ERR_EVENT_EN  {SF_DOMAIN, TYPE_RW, 2752, 26}
#define SCR_SF_CR52P_SCR_R52_GLOBAL_ERR_EVENT_EN  {SF_DOMAIN, TYPE_RW, 2784, 5}
#define SCR_SF_CR52P_SCR_R52_CORE_ERR_EVENT_CLR  {SF_DOMAIN, TYPE_RW, 2789, 4}
#define SCR_SF_CR52P_SCR_R52_GLOBAL_ERR_EVENT_CLR  {SF_DOMAIN, TYPE_RW, 2793, 1}
#define SCR_SF_R52_DBG_GASKET_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2794, 1}
#define SCR_SF_R52_DBG_GASKET_DBG_IRQ_STATUS_CLR  {SF_DOMAIN, TYPE_RW, 2795, 1}
#define SCR_SF_R52_DBG_GASKET_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2796, 1}
#define SCR_SF_SOC_DBG_GASKET_SF_UNCOR_IRQ_EN  {SF_DOMAIN, TYPE_RW, 2797, 1}
#define SCR_SF_SOC_DBG_GASKET_SF_UNCOR_IRQ_CLR  {SF_DOMAIN, TYPE_RW, 2798, 1}
#define SCR_SF_CR52P_AXI_F0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2816, 1}
#define SCR_SF_CR52P_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2816, 1}
#define SCR_SF_CR52P_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2816, 1}
#define SCR_SF_CR52P_AXI_P0_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2816, 1}
#define SCR_SF_CR52P_AXI_P0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2816, 1}
#define SCR_SF_CR52P_AXI_F1_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2817, 1}
#define SCR_SF_CR52P_AXI_M1_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2817, 1}
#define SCR_SF_CR52P_AXI_M1_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2817, 1}
#define SCR_SF_CR52P_AXI_P1_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2817, 1}
#define SCR_SF_CR52P_AXI_P1_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2817, 1}
#define SCR_SF_CR52P_AXI_F2_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2818, 1}
#define SCR_SF_CR52P_AXI_M2_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2818, 1}
#define SCR_SF_CR52P_AXI_M2_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2818, 1}
#define SCR_SF_CR52P_AXI_P2_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2818, 1}
#define SCR_SF_CR52P_AXI_P2_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2818, 1}
#define SCR_SF_CR52P_AXI_F3_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2819, 1}
#define SCR_SF_CR52P_AXI_M3_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2819, 1}
#define SCR_SF_CR52P_AXI_M3_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2819, 1}
#define SCR_SF_CR52P_AXI_P3_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2819, 1}
#define SCR_SF_CR52P_AXI_P3_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2819, 1}
#define SCR_SF_DMA_SF1_AHB_M0_HUSER_GEN_AHB_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2820, 1}
#define SCR_SF_DMA_SF1_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2820, 1}
#define SCR_SF_DMA_SF1_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2820, 1}
#define SCR_SF_DMA_SF1_AHB_M1_HUSER_GEN_AHB_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2820, 1}
#define SCR_SF_DMA_SF1_AXI_M1_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2820, 1}
#define SCR_SF_DMA_SF1_AXI_M1_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2820, 1}
#define SCR_SF_DMA_SF2_AHB_M0_HUSER_GEN_AHB_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2821, 1}
#define SCR_SF_DMA_SF2_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2821, 1}
#define SCR_SF_DMA_SF2_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2821, 1}
#define SCR_SF_DMA_SF2_AHB_M1_HUSER_GEN_AHB_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2821, 1}
#define SCR_SF_DMA_SF2_AXI_M1_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2821, 1}
#define SCR_SF_DMA_SF2_AXI_M1_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2821, 1}
#define SCR_SF_DPE_AHB_M_HUSER_GEN_AHB_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2822, 1}
#define SCR_SF_DPE_AXI_M_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2822, 1}
#define SCR_SF_DPE_AXI_M_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2822, 1}
#define SCR_SF_SEHC1_AXI_M_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2823, 1}
#define SCR_SF_SEHC1_AXI_M_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2823, 1}
#define SCR_SF_ENET1_AXI_M_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2824, 1}
#define SCR_SF_ENET1_AXI_M_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2824, 1}
#define SCR_SF_ENET2_AXI_M_AWUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2825, 1}
#define SCR_SF_ENET2_AXI_M_ARUSER_GEN_AXI_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2825, 1}
#define SCR_SF_PTB_MST_HUSER_GEN_AHB_GASKET_ERR_CLR  {SF_DOMAIN, TYPE_RW, 2826, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_A_SW_CFG  {SF_DOMAIN, TYPE_RW, 2848, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_A_SW_OVR_EN  {SF_DOMAIN, TYPE_RW, 2849, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_A_TEST_SEL_0  {SF_DOMAIN, TYPE_RW, 2850, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_A_TEST_SEL_1  {SF_DOMAIN, TYPE_RW, 2851, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_A_TESTEN  {SF_DOMAIN, TYPE_RW, 2852, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_E_SW_CFG  {SF_DOMAIN, TYPE_RW, 2880, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_E_SW_OVR_EN  {SF_DOMAIN, TYPE_RW, 2881, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_E_TEST_SEL_0  {SF_DOMAIN, TYPE_RW, 2882, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_E_TEST_SEL_1  {SF_DOMAIN, TYPE_RW, 2883, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_E_TESTEN  {SF_DOMAIN, TYPE_RW, 2884, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_K_SW_CFG  {SF_DOMAIN, TYPE_RW, 2912, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_K_SW_OVR_EN  {SF_DOMAIN, TYPE_RW, 2913, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_K_TEST_SEL_0  {SF_DOMAIN, TYPE_RW, 2914, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_K_TEST_SEL_1  {SF_DOMAIN, TYPE_RW, 2915, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_K_TESTEN  {SF_DOMAIN, TYPE_RW, 2916, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_M_SW_CFG  {SF_DOMAIN, TYPE_RW, 2944, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_M_SW_OVR_EN  {SF_DOMAIN, TYPE_RW, 2945, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_M_TEST_SEL_0  {SF_DOMAIN, TYPE_RW, 2946, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_M_TEST_SEL_1  {SF_DOMAIN, TYPE_RW, 2947, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_M_TESTEN  {SF_DOMAIN, TYPE_RW, 2948, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_S_SW_CFG  {SF_DOMAIN, TYPE_RW, 2976, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_S_SW_OVR_EN  {SF_DOMAIN, TYPE_RW, 2977, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_S_TEST_SEL_0  {SF_DOMAIN, TYPE_RW, 2978, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_S_TEST_SEL_1  {SF_DOMAIN, TYPE_RW, 2979, 1}
#define SCR_SF_DFT_MODULE_SF_PVSENSE_GPIO_S_TESTEN  {SF_DOMAIN, TYPE_RW, 2980, 1}
#define SCR_LP_EFUSEC_MANU_CFG_79_64  {LP_DOMAIN, TYPE_RO, 0, 16}
#define SCR_LP_EFUSEC_MANU_CFG_87_80  {LP_DOMAIN, TYPE_RO, 32, 8}
#define SCR_LP_EFUSEC_MISC_CFG_PROD_ENABLE  {LP_DOMAIN, TYPE_RO, 40, 1}
#define SCR_LP_EFUSEC_MANU_CFG_MFG_DISABLE  {LP_DOMAIN, TYPE_RO, 41, 1}
#define SCR_LP_EFUSEC_FA_CFG_FA_ENABLE  {LP_DOMAIN, TYPE_RO, 42, 1}
#define SCR_LP_EFUSEC_FUSE_READY  {LP_DOMAIN, TYPE_RO, 43, 1}
#define SCR_LP_EFUSEC_FUSE_LATCHED_PARTIAL  {LP_DOMAIN, TYPE_RO, 44, 1}
#define SCR_LP_CR52P_STANDBYWFI0  {LP_DOMAIN, TYPE_RO, 64, 1}
#define SCR_LP_CR52P_STANDBYWFI1  {LP_DOMAIN, TYPE_RO, 65, 1}
#define SCR_LP_CR52P_STANDBYWFI2  {LP_DOMAIN, TYPE_RO, 66, 1}
#define SCR_LP_CR52P_STANDBYWFI3  {LP_DOMAIN, TYPE_RO, 67, 1}
#define SCR_LP_CR5_SE_WFIPIPESTOPPED0  {LP_DOMAIN, TYPE_RO, 68, 1}
#define SCR_LP_CR5_LP_WFIPIPESTOPPED0  {LP_DOMAIN, TYPE_RO, 69, 1}
#define SCR_LP_FAB_LP_M_NL_0_I_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 96, 1}
#define SCR_LP_FAB_LP_NOC_LP_GPV_I_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 97, 1}
#define SCR_LP_FAB_LP_NOC_LP_SVREG_T_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 98, 1}
#define SCR_LP_FAB_LP_NOC_LP_SVREG_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 99, 1}
#define SCR_LP_FAB_LP_S_NL_0_T_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 100, 1}
#define SCR_LP_FAB_LP_S_NL_1_T_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 101, 1}
#define SCR_LP_AHB2AXI_CSSYS_TO_NOC_AP_M_0_I_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 102, 1}
#define SCR_LP_AHB2AXI_CSSYS_TO_NOC_AP_S_0_T_MAINNOPENDINGTRANS  {LP_DOMAIN, TYPE_RO, 103, 1}
#define SCR_LP_BTI_AXI_R5_LP_M0_CHN_IDLE  {LP_DOMAIN, TYPE_RO, 128, 1}
#define SCR_LP_BTI_AXI_R5_LP_M0_WRD_CHN_TIMEOUT  {LP_DOMAIN, TYPE_RO, 129, 1}
#define SCR_LP_BTI_AHB_R5_LP_H0_CHN_TIMEOUT  {LP_DOMAIN, TYPE_RO, 130, 1}
#define SCR_LP_BTI_AHB_R5_LP_H0_CHN_IDLE  {LP_DOMAIN, TYPE_RO, 131, 1}
#define SCR_LP_RTC_SS_PCLK_DIV_UPD_BUSY  {LP_DOMAIN, TYPE_RO, 160, 1}
#define SCR_LP_RTC_SS_PCLK_MUX_D0_ACTIVE  {LP_DOMAIN, TYPE_RO, 161, 1}
#define SCR_LP_RTC_SS_PCLK_MUX_D1_ACTIVE  {LP_DOMAIN, TYPE_RO, 162, 1}
#define SCR_LP_WES_PCLK_MUX_D0_ACTIVE  {LP_DOMAIN, TYPE_RO, 163, 1}
#define SCR_LP_WES_PCLK_MUX_D1_ACTIVE  {LP_DOMAIN, TYPE_RO, 164, 1}
#define SCR_LP_ADC7_PCLK_MUX_D0_ACTIVE  {LP_DOMAIN, TYPE_RO, 165, 1}
#define SCR_LP_ADC7_PCLK_MUX_D1_ACTIVE  {LP_DOMAIN, TYPE_RO, 166, 1}
#define SCR_LP_PLL_CK_MUX_LPP_D0_ACTIVE_0  {LP_DOMAIN, TYPE_RO, 167, 1}
#define SCR_LP_PLL_CK_MUX_LPP_D1_ACTIVE_0  {LP_DOMAIN, TYPE_RO, 168, 1}
#define SCR_LP_PLL_CK_MUX_LPP_D0_ACTIVE_1  {LP_DOMAIN, TYPE_RO, 169, 1}
#define SCR_LP_PLL_CK_MUX_LPP_D1_ACTIVE_1  {LP_DOMAIN, TYPE_RO, 170, 1}
#define SCR_LP_AXIUS_R5_LP_M0_O_SCR_RO_15_0  {LP_DOMAIN, TYPE_RO, 192, 16}
#define SCR_LP_AXIUS_R5_LP_M0_O_SCR_RO_28_16  {LP_DOMAIN, TYPE_RO, 224, 13}
#define SCR_LP_AXISG_R5_LP_P0_O_SCR_DEBUG_BIT_RO  {LP_DOMAIN, TYPE_RO, 256, 13}
#define SCR_LP_AXISG_AXB_LP_TO_AXB_R52A_O_SCR_DEBUG_BIT_RO  {LP_DOMAIN, TYPE_RO, 288, 14}
#define SCR_LP_CR5_LP_DBG_GASKET_DBG_IRQ_STATUS  {LP_DOMAIN, TYPE_RO, 320, 1}
#define SCR_LP_CR5_LP_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR  {LP_DOMAIN, TYPE_RO, 352, 1}
#define SCR_LP_CR5_LP_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR  {LP_DOMAIN, TYPE_RO, 353, 1}
#define SCR_LP_CR5_LP_AXI_P0_AWUSER_GEN_AXI_GASKET_ERR  {LP_DOMAIN, TYPE_RO, 354, 1}
#define SCR_LP_CR5_LP_AXI_P0_ARUSER_GEN_AXI_GASKET_ERR  {LP_DOMAIN, TYPE_RO, 355, 1}
#define SCR_LP_CR5_LP_AHB_P0_HUSER_GEN_AHB_GASKET_ERR  {LP_DOMAIN, TYPE_RO, 356, 1}
#define SCR_LP_CSSYS_AHB_M_HUSER_GEN_AHB_GASKET_ERR  {LP_DOMAIN, TYPE_RO, 357, 1}
#define SCR_LP_AMUX_ADC7_CH6P_CSEL_OUT  {LP_DOMAIN, TYPE_RO, 384, 4}
#define SCR_LP_AMUX_ADC7_CH6N_CSEL_OUT  {LP_DOMAIN, TYPE_RO, 388, 4}
#define SCR_LP_CR5_LP_CPU_HALT0  {LP_DOMAIN, TYPE_RW, 0, 1}
#define SCR_LP_CR5_LP_SCR_CR5_VICADDR_DISABLE  {LP_DOMAIN, TYPE_RW, 1, 1}
#define SCR_LP_CR5_LP_SCR_CR5_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 2, 1}
#define SCR_LP_CR5_LP_DBG_GASKET_HW_DBG_EN  {LP_DOMAIN, TYPE_RW, 3, 1}
#define SCR_LP_CR5_LP_DBG_GASKET_DBG_IRQ_STATUS_EN  {LP_DOMAIN, TYPE_RW, 4, 1}
#define SCR_LP_CR5_LP_DBG_GASKET_DBG_IRQ_STATUS_CLR  {LP_DOMAIN, TYPE_RW, 5, 1}
#define SCR_LP_CSSYS_TP_MAXDATASIZE  {LP_DOMAIN, TYPE_RW, 32, 5}
#define SCR_LP_CSSYS_SCR_TRACECLK_SEL  {LP_DOMAIN, TYPE_RW, 37, 1}
#define SCR_LP_RTC_SS_PCLK_DIV_DIV_NUM  {LP_DOMAIN, TYPE_RW, 64, 8}
#define SCR_LP_WES_ASE_LP_EN  {LP_DOMAIN, TYPE_RW, 96, 1}
#define SCR_LP_WES_PCLK_MUX_SELECT_24M  {LP_DOMAIN, TYPE_RW, 97, 1}
#define SCR_LP_ADC7_PCLK_MUX_SELECT_24M  {LP_DOMAIN, TYPE_RW, 98, 1}
#define SCR_LP_CANFD_EXT_CLK_P2MP_SCR_SEL_CANFD_EXT_CLK  {LP_DOMAIN, TYPE_RW, 128, 1}
#define SCR_LP_CANFD1_STOP_DOZE_SEL  {LP_DOMAIN, TYPE_RW, 160, 1}
#define SCR_LP_CANFD2_STOP_DOZE_SEL  {LP_DOMAIN, TYPE_RW, 192, 1}
#define SCR_LP_SOC_DBG_GASKET_LP_SW_CORE_DBG_EN  {LP_DOMAIN, TYPE_RW, 224, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_I2C1  {LP_DOMAIN, TYPE_RW, 232, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_UART1  {LP_DOMAIN, TYPE_RW, 240, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_UART2  {LP_DOMAIN, TYPE_RW, 248, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_SPI1  {LP_DOMAIN, TYPE_RW, 256, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_SPI2  {LP_DOMAIN, TYPE_RW, 264, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_BTM1  {LP_DOMAIN, TYPE_RW, 272, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_BTM2  {LP_DOMAIN, TYPE_RW, 280, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_WDT1  {LP_DOMAIN, TYPE_RW, 288, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_WDT9  {LP_DOMAIN, TYPE_RW, 296, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_ADC7  {LP_DOMAIN, TYPE_RW, 304, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_CANFD1  {LP_DOMAIN, TYPE_RW, 312, 6}
#define SCR_LP_SOC_DBG_GASKET_LP_IP_DBG_EN_CANFD2  {LP_DOMAIN, TYPE_RW, 320, 6}
#define SCR_LP_BTI_AXI_R5_LP_M0_TIMEOUT_DIV  {LP_DOMAIN, TYPE_RW, 352, 8}
#define SCR_LP_BTI_AXI_R5_LP_M0_BTI_EN  {LP_DOMAIN, TYPE_RW, 360, 1}
#define SCR_LP_BTI_AHB_R5_LP_H0_TIMEOUT_DIV  {LP_DOMAIN, TYPE_RW, 384, 8}
#define SCR_LP_BTI_AHB_R5_LP_H0_BTI_EN  {LP_DOMAIN, TYPE_RW, 392, 1}
#define SCR_LP_RW_RESERVED_ADDR13  {LP_DOMAIN, TYPE_RW, 416, 32}
#define SCR_LP_REF_GEN_LPP_BYPSS_EN  {LP_DOMAIN, TYPE_RW, 480, 1}
#define SCR_LP_REF_GEN_LPP_LPM_EN  {LP_DOMAIN, TYPE_RW, 481, 1}
#define SCR_LP_LDO50TO33_DFT_MUX_IO_LPP_ATEST_SEL  {LP_DOMAIN, TYPE_RW, 512, 2}
#define SCR_LP_LDO50TO33_DFT_MUX_IO_LPP_ATESTEN  {LP_DOMAIN, TYPE_RW, 514, 1}
#define SCR_LP_LDO50TO33_DFT_MUX_IO_LPP_SW_OVR_EN  {LP_DOMAIN, TYPE_RW, 515, 1}
#define SCR_LP_LDO50TO33_DFT_MUX_IO_LPP_SW_CFG  {LP_DOMAIN, TYPE_RW, 516, 1}
#define SCR_LP_LDO50TO33_DFT_MUX_IO_LPP_REG_EN  {LP_DOMAIN, TYPE_RW, 517, 1}
#define SCR_LP_LDO50TO33_DFT_MUX_IO_LPP_TR  {LP_DOMAIN, TYPE_RW, 518, 6}
#define SCR_LP_DFT_MUX_COMB_IO_LPP_TEST_EN  {LP_DOMAIN, TYPE_RW, 524, 1}
#define SCR_LP_DFT_MUX_COMB_IO_LPP_TEST_SEL  {LP_DOMAIN, TYPE_RW, 525, 1}
#define SCR_LP_SCAN_MUX_BGR33_LP_REG0  {LP_DOMAIN, TYPE_RW, 544, 11}
#define SCR_LP_SCAN_MUX_BGR33_LP_TEST  {LP_DOMAIN, TYPE_RW, 555, 3}
#define SCR_LP_SCAN_MUX_BGR33_LP_BGSEL  {LP_DOMAIN, TYPE_RW, 558, 5}
#define SCR_LP_BGR33_LP_TRIM_SEL  {LP_DOMAIN, TYPE_RW, 563, 1}
#define SCR_LP_APD_A_LA0_CTRL  {LP_DOMAIN, TYPE_RW, 576, 4}
#define SCR_LP_APD_A_LA1_CTRL  {LP_DOMAIN, TYPE_RW, 580, 4}
#define SCR_LP_APD_A_LA2_CTRL  {LP_DOMAIN, TYPE_RW, 584, 4}
#define SCR_LP_APD_A_LA3_CTRL  {LP_DOMAIN, TYPE_RW, 588, 4}
#define SCR_LP_APD_A_LA4_CTRL  {LP_DOMAIN, TYPE_RW, 592, 4}
#define SCR_LP_APD_A_LA5_CTRL  {LP_DOMAIN, TYPE_RW, 596, 4}
#define SCR_LP_APD_A_LA6_CTRL  {LP_DOMAIN, TYPE_RW, 600, 4}
#define SCR_LP_APD_A_LA7_CTRL  {LP_DOMAIN, TYPE_RW, 604, 4}
#define SCR_LP_APD_A_LA8_CTRL  {LP_DOMAIN, TYPE_RW, 608, 4}
#define SCR_LP_APD_A_LA9_CTRL  {LP_DOMAIN, TYPE_RW, 612, 4}
#define SCR_LP_APD_A_LA10_CTRL  {LP_DOMAIN, TYPE_RW, 616, 4}
#define SCR_LP_APD_A_LA11_CTRL  {LP_DOMAIN, TYPE_RW, 620, 4}
#define SCR_LP_APD_A_LA12_CTRL  {LP_DOMAIN, TYPE_RW, 624, 4}
#define SCR_LP_APD_A_LA13_CTRL  {LP_DOMAIN, TYPE_RW, 628, 4}
#define SCR_LP_APD_A_LA14_CTRL  {LP_DOMAIN, TYPE_RW, 632, 4}
#define SCR_LP_APD_A_LA15_CTRL  {LP_DOMAIN, TYPE_RW, 636, 4}
#define SCR_LP_APD_A_LA16_CTRL  {LP_DOMAIN, TYPE_RW, 640, 4}
#define SCR_LP_APD_A_LA17_CTRL  {LP_DOMAIN, TYPE_RW, 644, 4}
#define SCR_LP_APD_A_LA18_CTRL  {LP_DOMAIN, TYPE_RW, 648, 4}
#define SCR_LP_APD_A_LA19_CTRL  {LP_DOMAIN, TYPE_RW, 652, 4}
#define SCR_LP_APD_A_LA20_CTRL  {LP_DOMAIN, TYPE_RW, 656, 4}
#define SCR_LP_APD_A_LA21_CTRL  {LP_DOMAIN, TYPE_RW, 660, 4}
#define SCR_LP_APD_A_LA22_CTRL  {LP_DOMAIN, TYPE_RW, 664, 4}
#define SCR_LP_APD_A_LA23_CTRL  {LP_DOMAIN, TYPE_RW, 668, 4}
#define SCR_LP_APD_A_LA24_CTRL  {LP_DOMAIN, TYPE_RW, 672, 4}
#define SCR_LP_APD_A_LA25_CTRL  {LP_DOMAIN, TYPE_RW, 676, 4}
#define SCR_LP_APD_A_LA26_CTRL  {LP_DOMAIN, TYPE_RW, 680, 4}
#define SCR_LP_APD_A_LA27_CTRL  {LP_DOMAIN, TYPE_RW, 684, 4}
#define SCR_LP_AMSEL_ADC7_CH6N_CSEL3_MUX_D0  {LP_DOMAIN, TYPE_RW, 704, 1}
#define SCR_LP_AMSEL_ADC7_CH6N_CSEL3_MUX_S  {LP_DOMAIN, TYPE_RW, 705, 1}
#define SCR_LP_AMSEL_ADC7_CH6P_CSEL3_MUX_D0  {LP_DOMAIN, TYPE_RW, 706, 1}
#define SCR_LP_AMSEL_ADC7_CH6P_CSEL3_MUX_S  {LP_DOMAIN, TYPE_RW, 707, 1}
#define SCR_LP_DFT_MUX_AMUX_TEST_ADC7_CH6P_TEST  {LP_DOMAIN, TYPE_RW, 708, 2}
#define SCR_LP_DFT_MUX_AMUX_TEST_ADC7_CH6N_TEST  {LP_DOMAIN, TYPE_RW, 710, 2}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_J_SW_CFG  {LP_DOMAIN, TYPE_RW, 736, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_J_SW_OVR_EN  {LP_DOMAIN, TYPE_RW, 737, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_J_TEST_SEL_0  {LP_DOMAIN, TYPE_RW, 738, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_J_TEST_SEL_1  {LP_DOMAIN, TYPE_RW, 739, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_J_TESTEN  {LP_DOMAIN, TYPE_RW, 740, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LA_SW_CFG  {LP_DOMAIN, TYPE_RW, 768, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LA_SW_OVR_EN  {LP_DOMAIN, TYPE_RW, 769, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LA_TEST_SEL_0  {LP_DOMAIN, TYPE_RW, 770, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LA_TEST_SEL_1  {LP_DOMAIN, TYPE_RW, 771, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LA_TESTEN  {LP_DOMAIN, TYPE_RW, 772, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LD_SW_CFG  {LP_DOMAIN, TYPE_RW, 800, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LD_SW_OVR_EN  {LP_DOMAIN, TYPE_RW, 801, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LD_TEST_SEL_0  {LP_DOMAIN, TYPE_RW, 802, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LD_TEST_SEL_1  {LP_DOMAIN, TYPE_RW, 803, 1}
#define SCR_LP_DFT_MODULE_LPP_PVSENSE_GPIO_LD_TESTEN  {LP_DOMAIN, TYPE_RW, 804, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_A  {LP_DOMAIN, TYPE_RW, 832, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_G  {LP_DOMAIN, TYPE_RW, 833, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_H  {LP_DOMAIN, TYPE_RW, 834, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_K  {LP_DOMAIN, TYPE_RW, 835, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_M  {LP_DOMAIN, TYPE_RW, 836, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_S  {LP_DOMAIN, TYPE_RW, 837, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_X  {LP_DOMAIN, TYPE_RW, 838, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_GPIO_E  {LP_DOMAIN, TYPE_RW, 839, 1}
#define SCR_LP_DFT_MODULE_SF_IO_RET_VAL_LDO50TO3317  {LP_DOMAIN, TYPE_RW, 840, 1}
#define SCR_LP_BTI_AXI_R5_LP_M0_UNCOR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 864, 1}
#define SCR_LP_BTI_AXI_R5_LP_M0_UNCOR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 865, 1}
#define SCR_LP_BTI_AHB_R5_LP_H0_UNCOR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 866, 1}
#define SCR_LP_BTI_AHB_R5_LP_H0_UNCOR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 867, 1}
#define SCR_LP_AHB2APB1_COR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 868, 1}
#define SCR_LP_AHB2APB1_UNCOR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 869, 1}
#define SCR_LP_AHB2APB1_COR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 870, 1}
#define SCR_LP_AHB2APB1_UNCOR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 871, 1}
#define SCR_LP_AHB2APB2_COR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 872, 1}
#define SCR_LP_AHB2APB2_UNCOR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 873, 1}
#define SCR_LP_AHB2APB2_COR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 874, 1}
#define SCR_LP_AHB2APB2_UNCOR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 875, 1}
#define SCR_LP_APB2TO1_APBMUX2_I_LSP_CMP_EN  {LP_DOMAIN, TYPE_RW, 876, 1}
#define SCR_LP_APB2TO1_APBMUX2_I_UNCORR_IRQ_MSK  {LP_DOMAIN, TYPE_RW, 877, 1}
#define SCR_LP_APB2TO1_APBMUX2_I_UNCORR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 878, 1}
#define SCR_LP_AAPB_MST_APBMUX1_TO_RTC_SS_SRC_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 879, 1}
#define SCR_LP_AAPB_MST_APBMUX1_TO_RTC_SS_SRC_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 880, 1}
#define SCR_LP_AAPB_SLV_APBMUX1_TO_RTC_SS_DST_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 881, 1}
#define SCR_LP_AAPB_SLV_APBMUX1_TO_RTC_SS_DST_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 882, 1}
#define SCR_LP_AAPB_MST_APBMUX1_TO_RTC_LBIST_SRC_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 883, 1}
#define SCR_LP_AAPB_MST_APBMUX1_TO_RTC_LBIST_SRC_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 884, 1}
#define SCR_LP_AAPB_SLV_APBMUX1_TO_RTC_LBIST_DST_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 885, 1}
#define SCR_LP_AAPB_SLV_APBMUX1_TO_RTC_LBIST_DST_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 886, 1}
#define SCR_LP_AAPB_MST_APBMUX2_TO_LPP_AON_24M_SRC_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 887, 1}
#define SCR_LP_AAPB_MST_APBMUX2_TO_LPP_AON_24M_SRC_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 888, 1}
#define SCR_LP_AAPB_SLV_APBMUX2_TO_LPP_AON_24M_DST_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 889, 1}
#define SCR_LP_AAPB_SLV_APBMUX2_TO_LPP_AON_24M_DST_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 890, 1}
#define SCR_LP_AAPB_SLV_MAC_TO_LPP_MIX_DST_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 891, 1}
#define SCR_LP_AAPB_SLV_MAC_TO_LPP_MIX_DST_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 892, 1}
#define SCR_LP_AAPB_SLV_XBSF_TO_APBMUX2_DST_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 893, 1}
#define SCR_LP_AAPB_SLV_XBSF_TO_APBMUX2_DST_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 894, 1}
#define SCR_LP_AXIUS_R5_LP_M0_I_SCR_UNC_IRQ_EN  {LP_DOMAIN, TYPE_RW, 895, 1}
#define SCR_LP_AXIUS_R5_LP_M0_I_SCR_UNC_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 896, 1}
#define SCR_LP_AXISG_R5_LP_P0_I_SCR_UNC_IRQ_EN  {LP_DOMAIN, TYPE_RW, 897, 1}
#define SCR_LP_AXISG_R5_LP_P0_I_SCR_UNC_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 898, 1}
#define SCR_LP_AXISG_AXB_LP_TO_AXB_R52A_I_SCR_UNC_IRQ_EN  {LP_DOMAIN, TYPE_RW, 899, 1}
#define SCR_LP_AXISG_AXB_LP_TO_AXB_R52A_I_SCR_UNC_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 900, 1}
#define SCR_LP_CR5_LP_DBG_GASKET_UNCOR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 901, 1}
#define SCR_LP_CR5_LP_DBG_GASKET_UNCOR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 902, 1}
#define SCR_LP_SOC_DBG_GASKET_LP_UNCOR_IRQ_EN  {LP_DOMAIN, TYPE_RW, 903, 1}
#define SCR_LP_SOC_DBG_GASKET_LP_UNCOR_IRQ_CLR  {LP_DOMAIN, TYPE_RW, 904, 1}
#define SCR_LP_CR5_LP_AXI_M0_AWUSER_GEN_AXI_GASKET_ERR_CLR  {LP_DOMAIN, TYPE_RW, 905, 1}
#define SCR_LP_CR5_LP_AXI_M0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {LP_DOMAIN, TYPE_RW, 905, 1}
#define SCR_LP_CR5_LP_AXI_P0_AWUSER_GEN_AXI_GASKET_ERR_CLR  {LP_DOMAIN, TYPE_RW, 905, 1}
#define SCR_LP_CR5_LP_AXI_P0_ARUSER_GEN_AXI_GASKET_ERR_CLR  {LP_DOMAIN, TYPE_RW, 905, 1}
#define SCR_LP_CR5_LP_AHB_P0_HUSER_GEN_AHB_GASKET_ERR_CLR  {LP_DOMAIN, TYPE_RW, 905, 1}
#define SCR_LP_CSSYS_AHB_M_HUSER_GEN_AHB_GASKET_ERR_CLR  {LP_DOMAIN, TYPE_RW, 906, 1}
#define SCR_LP_AAPB_FAB_LP_SRC_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 907, 1}
#define SCR_LP_AAPB_FAB_LP_SRC_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 908, 1}
#define SCR_LP_AAPB_FAB_LP_DST_IRQ_ENB  {LP_DOMAIN, TYPE_RW, 909, 1}
#define SCR_LP_AAPB_FAB_LP_DST_UNCERR_CLR  {LP_DOMAIN, TYPE_RW, 910, 1}
#define SCR_LP_SOC_WFI_GASKET_SCR_CORE_WFI_IGNORE  {LP_DOMAIN, TYPE_RW, 928, 6}
#define SCR_LP_CR52P_DBGEN0  {LP_DOMAIN, TYPE_L16, 0, 1}
#define SCR_LP_CR52P_NIDEN0  {LP_DOMAIN, TYPE_L16, 1, 1}
#define SCR_LP_CR52P_HIDEN0  {LP_DOMAIN, TYPE_L16, 2, 1}
#define SCR_LP_CR52P_HNIDEN0  {LP_DOMAIN, TYPE_L16, 3, 1}
#define SCR_LP_CR52P_DBGEN1  {LP_DOMAIN, TYPE_L16, 4, 1}
#define SCR_LP_CR52P_NIDEN1  {LP_DOMAIN, TYPE_L16, 5, 1}
#define SCR_LP_CR52P_HIDEN1  {LP_DOMAIN, TYPE_L16, 6, 1}
#define SCR_LP_CR52P_HNIDEN1  {LP_DOMAIN, TYPE_L16, 7, 1}
#define SCR_LP_CR52P_DBGEN2  {LP_DOMAIN, TYPE_L16, 8, 1}
#define SCR_LP_CR52P_NIDEN2  {LP_DOMAIN, TYPE_L16, 9, 1}
#define SCR_LP_CR52P_HIDEN2  {LP_DOMAIN, TYPE_L16, 10, 1}
#define SCR_LP_CR52P_HNIDEN2  {LP_DOMAIN, TYPE_L16, 11, 1}
#define SCR_LP_CR52P_DBGEN3  {LP_DOMAIN, TYPE_L16, 12, 1}
#define SCR_LP_CR52P_NIDEN3  {LP_DOMAIN, TYPE_L16, 13, 1}
#define SCR_LP_CR52P_HIDEN3  {LP_DOMAIN, TYPE_L16, 14, 1}
#define SCR_LP_CR52P_HNIDEN3  {LP_DOMAIN, TYPE_L16, 15, 1}
#define SCR_LP_CR5_LP_DBGEN0  {LP_DOMAIN, TYPE_L16, 32, 1}
#define SCR_LP_CR5_LP_NIDEN0  {LP_DOMAIN, TYPE_L16, 33, 1}
#define SCR_LP_CR5_SE_DBGEN0  {LP_DOMAIN, TYPE_L16, 64, 1}
#define SCR_LP_CR5_SE_NIDEN0  {LP_DOMAIN, TYPE_L16, 65, 1}
#define SCR_LP_CSSYS_DBGEN  {LP_DOMAIN, TYPE_L16, 96, 1}
#define SCR_LP_CSSYS_NIDEN  {LP_DOMAIN, TYPE_L16, 97, 1}
#define SCR_LP_CSSYS_AP_EN  {LP_DOMAIN, TYPE_L16, 98, 1}
#define SCR_LP_CSSYS_AP_SECURE_EN  {LP_DOMAIN, TYPE_L16, 99, 1}
#define SCR_LP_IRAM_LP_ECC_DISABLE  {LP_DOMAIN, TYPE_L16, 128, 1}
#define SCR_LP_MRAM5_ECC_DISABLE  {LP_DOMAIN, TYPE_L16, 129, 1}
#define SCR_LP_FMMU_LP_AW_ADDR_OFFSET  {LP_DOMAIN, TYPE_L31, 0, 20}
#define SCR_LP_FMMU_LP_AW_REMAP_EN  {LP_DOMAIN, TYPE_L31, 20, 1}
#define SCR_LP_FMMU_LP_AR_ADDR_OFFSET  {LP_DOMAIN, TYPE_L31, 0, 20}
#define SCR_LP_FMMU_LP_AR_REMAP_EN  {LP_DOMAIN, TYPE_L31, 20, 1}
#define SCR_LP_R52P_CFG_VECTABLE0  {LP_DOMAIN, TYPE_L31, 32, 27}
#define SCR_LP_R52P_C0_VECTABLE_CFG_EN  {LP_DOMAIN, TYPE_L31, 59, 1}
#define SCR_LP_REMAP_CR5_SE_ADDR_OFFSET  {LP_DOMAIN, TYPE_L31, 64, 20}
#define SCR_LP_REMAP_CR5_SE_REMAP_EN  {LP_DOMAIN, TYPE_L31, 84, 1}

#ifdef __cplusplus
}
#endif
#endif /* MCALSCRBITS_H */
/* End of file */
